1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure, device configuration and improved process for fabricating a trenched semiconductor power device with improved increased cell density by reducing a gate to source contact critical dimension (CD) requirement.
2. Description of the Related Art
In order to further increase the cell density in a semiconductor power device, the MOSFET devices are manufactured with trenched source contact plugs with the plugs formed with tungsten to reduce the distance between the gate and the source contact. Specifically, the Applicant of this Patent Application has filed another patent application Ser. No. 11/147,075 on Jun. 6, 2005 to improve the cell density by reducing the distance between the source contacts 45 and the trenched gates 20. An improved configuration of a MOSFET device is shown in FIG. 1 wherein the distance between the source contacts 45 and the trenched gates 20 are reduced by placing the source contact 45 in the source-body contact trenches opened in an oxide layer 35. As shown in FIG. 1A, the source-body contact 45 in the trenches extend into the body regions 25 thus contacting both the source regions 30 and the body regions 25 to provide improved and more reliable electric contacts. The difficulties of the conventional technologies to further increase the cell density due to the requirement of a large critical dimension (CD) between the source contacts and the trench gates is relaxed.
However, with tungsten plugs implemented as source and gate contact, there are still additional technical challenges confronted with such device configuration and manufacturing processes. Specifically, before refilling the contact trenches with tungsten plug or aluminum alloy, contact silicon etch is required after the oxide-etch is completed to form the contact trenches through the insulating dielectric layer(s). Potential problems may arise in carrying out the contact silicon etch due to the possibility of etching through the polysilicon gate unless special layout are prearranged to prevent such possibilities. The etch through problem may likely occur due to the formation of the polysilicon seam or holes in the middle portion of the poly-gate during the process of polysilicon deposition as that shown in FIG. 1A. If the etch through occurs, the tungsten plug or aluminum alloy may short through the gate oxide and drain at the trench bottom thus causing device reliability problems.
Furthermore, the contact silicon etch may etch through trench gate polysilicon with a T-intersection layout due to polysilicon hole and seam formation during the process of a polysilicon deposition in certain trenched gate area as shown in FIGS. 1B and 1C as the result of two dimensional polysilicon deposition. With such etch through holes penetrated through the polysilicon gates, the tungsten plug when filling in the contact trenches also filling into such etch-through holes thus generating an electrical short circuit through the gate oxide and the drain at trench bottom shown in FIGS. 1D to 1F. The etch-through problem with the holes penetrating through the polysilicon layer thus often causes a gate-to-drain shortage and raising device performance reliability issues.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations.